Method and apparatus for encoding lba information into the parity of a ldpc system

ABSTRACT

Systems and methods for encoding and decoding at least one logical block address in a low density parity check (LDPC) are disclosed. These systems and methods can include selecting a LDPC Code matrix and a parity check matrix wherein the LDPC Code matrix and the parity check matrix have an orthogonal relationship. These systems and methods may further include encoding a data element using at least some of the LBA bits in the parity bits in a LDPC codeword creating a parity vector using the at least some of the LBA bits in the LDPC codeword.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC 119(e) to U.S. provisionalApplication Ser. No. 61/246,002, filed on Sep. 25, 2009, and which isincorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

The present application relates generally to Logical Block Addressesand, more specifically, to the use of Logical Block Addresses in variousencoders and decoders.

BACKGROUND OF THE INVENTION

A low-density parity-check (LDPC) code is a linear error correctingcode. It may be used as a method of transmitting a message over a noisytransmission channel, and is constructed using a sparse bipartite graph.

LDPC codes are capacity-approaching codes, which means that practicalconstructions exist that allow the noise threshold to be set very close(or even arbitrarily close on the binary erasure channel (BEC)) to thetheoretical maximum (the Shannon limit) for a symmetric memory-lesschannel. The noise threshold defines an upper bound for the channelnoise, up to which the probability of lost information can be made assmall as desired.

Using iterative belief propagation techniques, LDPC codes can be decodedin time linear to their block length.

SUMMARY OF THE INVENTION

In one embodiment, a method of encoding is disclosed that includes atleast one logical block address in a low density parity check (LDPC).This method can include selecting a LDPC Code matrix and a parity checkmatrix, wherein the LDPC Code matrix and the parity check matrix have anorthogonal relationship, encoding a logical block address (LBA) using atleast some of the LBA bits in the parity bits in a LDPC codeword, andcreating a parity vector using the at least some of the LBA bits in theLDPC codeword.

Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, itmay be advantageous to set forth definitions of certain words andphrases used throughout this patent document: the terms “include” and“comprise,” as well as derivatives thereof, mean inclusion withoutlimitation; the term “or,” is inclusive, meaning and/or; the phrases“associated with” and “associated therewith,” as well as derivativesthereof, may mean to include, be included within, interconnect with,contain, be contained within, connect to or with, couple to or with, becommunicable with, cooperate with, interleave, juxtapose, be proximateto, be bound to or with, have, have a property of, or the like; and theterm “controller” means any device, system or part thereof that controlsat least one operation, such a device may be implemented in hardware,firmware or software, or some combination of at least two of the same.It should be noted that the functionality associated with any particularcontroller may be centralized or distributed, whether locally orremotely. Definitions for certain words and phrases are providedthroughout this patent document, those of ordinary skill in the artshould understand that in many, if not most instances, such definitionsapply to prior, as well as future uses of such defined words andphrases.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure and itsadvantages, reference is now made to the following description taken inconjunction with the accompanying drawings, in which like referencenumerals represent like parts:

FIG. 1 illustrates LBA usage in a LDPC encoder according to an exemplaryembodiment of the disclosure;

FIG. 2 illustrates LBA usage in a LDPC decoder according to an exemplaryembodiment of the disclosure; and

FIG. 3 is a flowchart of one method of using the disclosed embodiments.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1 through 3, discussed below, and the various embodiments used todescribe the principles of the present disclosure in this patentdocument are by way of illustration only and should not be construed inany way to limit the scope of the disclosure. Those skilled in the artwill understand that the principles of the present disclosure may beimplemented in any suitably arranged encoder and/or decoder.

Logical Block Address (LBA) is a field received from the host thatuniquely identifies each sector. It is given the same protection as theuser data with respect to the LDPC code. The LBA is not written to thedisk and is supplied by the host to the encoder during a write and tothe decoder during a read.

The LDPC encoder takes the output of the error detection and correction(EDC) block with the LBA specified on a parallel path. The encodergenerates parity using the LBA as normal user data. This LBA seededparity is appended to the user data to be written to the disk, but theLBA field is not.

Likewise, the LDPC decoder takes the LBA as an input on a parallel pathalong with the de-interleaved soft output Viterbi algorithm (SOVA)extrinsic information. The LBA is then included in the LDPC decodefunction. If the LDPC decode function does not converge, a fault is sentto the host. When the LDPC decode function converges to what is believedto be the correct codeword, the decoded LBA is compared to the expectedLBA. If the two values do not agree, a fault is sent to the host. If thetwo values do agree, the codeword is sent to the EDC syndrome check,which provides another level of protection.

The LBA is a 40 bit field. For 512 byte sectors, the full 40 bits isused to identify the sector. For 4K byte sectors, 38 bits are used toidentify each sector and 2 bits are used to identify the 1 K byte blockswithin a sector. In a 1 K block, the two 512 byte codewords have thesame LBA.

Consider an LDPC Code with systematic generator matrix G, given byEquation 1 below:

$\begin{matrix}{G = {\begin{bmatrix}I & 0 \\G_{p} & G_{L} \\0 & I\end{bmatrix}.}} & \left\lbrack {{Eqn}.\mspace{14mu} 1} \right\rbrack\end{matrix}$

The corresponding parity check matrix, H, is then specified by Equations2 and 3 below:

H=[A B Λ]  [Eqn. 2]

where

Λ=[I I I I]^(T)  [Eqn. 3]

The relationship between these matrices results from the requirementthat they must be orthogonal as specified by Equation 4 below:

$\begin{matrix}{{HG} = \left. 0\Rightarrow\begin{matrix}{G_{p} = {{- B^{- 1}}A}} \\{G_{L} = {{- B^{- 1}}{\Lambda.}}}\end{matrix} \right.} & \left\lbrack {{Eqn}.\mspace{14mu} 4} \right\rbrack\end{matrix}$

Thus, given a parity check matrix, H, this expression can be used tocalculate the generator matrix. When this process is followed, theencoding process may be represented as described below.

Let u be the user data coming from the EDC Encode block, let L be theLBA bits and let p be the LBA encoded parity. Then, the LDPC codeword isgiven by the following expression, indicated as equation 5.

$\begin{matrix}{{c = {{G\begin{bmatrix}u \\L\end{bmatrix}} = {\left\lceil \begin{matrix}u \\p \\L\end{matrix} \right\rceil = \left\lceil \begin{matrix}u \\{{G_{L}L} + {G_{p}u}} \\L\end{matrix} \right\rceil}}},} & \left\lbrack {{Eqn}.\mspace{14mu} 5} \right\rbrack \\{where} & \; \\{p = {{G_{L}L} + {G_{p}{u.}}}} & \left\lbrack {{Eqn}.\mspace{14mu} 6} \right\rbrack\end{matrix}$

Although L is officially a part of the codeword, L is may not be storedon the disk. It is needed by the LDPC decoder, but it may travel adifferent path to get there.

As can be seen in Equations 5 and 6 above, the parity calculationrequires two components. The first component is dependent on the LEA asshown by Equation 7 below:

G_(o)=G_(L)L  [Eqn. 7]

This component uses GL, a column vector of 4 circulant matrices, toprecompute the initial parity vector, po. This matrix is represented asshown by Equation 8 below:

$\begin{matrix}{G_{L} = {\begin{bmatrix}G_{L\; 1} \\G_{L\; 2} \\G_{L\; 3} \\G_{L\; 4}\end{bmatrix} = {\begin{bmatrix}g_{0,0}^{(L)} & \ldots & g_{0,127}^{(L)} \\\vdots & \ldots & \vdots \\g_{511,0}^{(L)} & \ldots & g_{511,127}^{(L)}\end{bmatrix}.}}} & \left\lbrack {{Eqn}.\mspace{14mu} 8} \right\rbrack\end{matrix}$

Because the submatrices G are circulants. The calculations can beimplemented by shift registers. Four vectors are sufficient to representthis matrix, given as {g_(L1), g_(L2), g_(L)3, g_(L)4}

where the following relationships are shown by Equation set 9 below:

g_(L1)=(g_(0,0) ^((L)), . . . , g_(128,127) ^((L)))

g_(L2)=(g_(128,0) ^((L)), . . . , g_(0,127) ^((L)))

g_(L3)=(g_(256,0) ^((L)), . . . , g_(256,127) ^((L)))

g_(L4)=(g_(384,0) ^((L)), . . . , g_(384,127) ^((L)))  [Eqn. 9]

The LBA mathematically represents a vector of length 128 where the first40 bits are the LBA field and the other bits are zero as shown inEquation 10 below:

L=[l₀, . . . , l₃₉, 0, . . . , 0]^(T)  [Eqn. 10]

An example of the required operations for the first 128 bits of theinitial parity vector is shown as Equation set 11 below:

$\begin{matrix}{{p_{o,0} = {{l_{0}g_{0,0}} + {l_{1}g_{0,1}} + \ldots + {l_{39}g_{0,39}}}}{p_{o,1} = {{l_{0}g_{0,127}} + {l_{1}g_{0,0}} + \ldots + {l_{39}g_{0,38}}}}{p_{o,2} = {{l_{0}g_{0,126}} + {l_{1}g_{0,127}} + \ldots + {l_{39}g_{0,37}}}}\vdots {p_{o,127} = {{l_{0}g_{0,1}} + {l_{1}g_{0,2}} + \ldots + {l_{39}{g_{0,40}.}}}}} & \left\lbrack {{Eqn}.\mspace{14mu} 11} \right\rbrack\end{matrix}$

The second component of the parity is calculated the same as the currentencoder. The final result is obtained by performing modulo two additionof the result to the initial parity vector shown in Equation 12 below:

p=p _(o) +G _(p) u  [Eqn. 12]

The LBA decoding operation utilizes the parity check matrix, H,represented as Equation 13 below:

$\begin{matrix}{H = {\begin{bmatrix}H_{0,0} & \ldots & H_{0,37} & I \\H_{1,0} & \ldots & H_{1,37} & I \\H_{2,0} & \ldots & H_{2,37} & I \\I & \ldots & I & I\end{bmatrix}.}} & \left\lbrack {{Eqn}.\mspace{14mu} 13} \right\rbrack\end{matrix}$

With this matrix, the decoder implements 4 layers and 39 circulantcolumns. The last circulant column, corresponding to the LBA field, willonly have 40 log likelihood ratio (LLR) values that participate in thedecoding operation. The other values could be treated as zero pads.Since they are always zeros, no hardware need be added representingthese locations.

The LBA locations can be pinned by using LLR values 127 or −128 torepresent 0 or 1, respectively. Alternatively, the LBA locations can bebiased with large values 126 or −127 to represent 0 or 1, respectively.In this case, the LLR values would be allowed to float, and if a validcodeword results, the LBA portion can be compared with the expected LBAvalues to determine if an error occurs in the LBA portion. Both theseoptions should be supported, and the firmware should be able to selectthe desired option by a register flag.

The matrices given above were in standard format. For implementation,these matrices will be converted to subcirculant form with 32 sublayersand parallelism 4. The locations of the LBA bits are not changed. TheLBA bits are maintained as the first forty bit positions within the LBAcirculant column.

In particular embodiments, for the purposes of verification, verify_encand verify_dec programs are available for block level validation.Additionally, verify_lis is available for LIS level validation.

FIG. 1 is an exemplary diagram of a LDPC encoder 100 which may be usedconsistent with the present disclosure. As shown in FIG. 1, aphased-locked loop (PLL) encode block 102 feeds a signal into an EDCEncode block 104. The EDC Encode block 104 is coupled to PRBS block 106.The EDC Encode block 104 outputs a signal into a LDPC encode block 108.Both the EDC Encode block 104 and the LDPC encode block 108 receive theLBA. The LDPC encode block 108 outputs a signal into a write path 110.

FIG. 2 is an exemplary diagram of a LDPC decoder 200 which may be usedconsistent with the present disclosure. A P−1 block 202 introduces asignal into a LDPC decoder 204. The LDPC decoder 204 outputs the decodedsignal into an EDC syndrome check 206. Both the LDPC decoder 204 and theEDC syndrome check 206 receive a signal from the LBA.

FIG. 3 is a flowchart 300 of one method of using the disclosed systemsand methods. In block 302, an LDPC code matrix is selected. In block304, there is a selection of a parity check matrix with an orthogonalrelationship to the LDPC code matrix. In block 306, there is an encodingof a data element using the LDPC code matrix and the parity checkmatrix. In block 308, there is a creation of a parity vector using atleast some of the LBA bits in a LDPC codeword.

It may be advantageous to set forth definitions of certain words andphrases used in this patent document. The term “couple” and itsderivatives refer to any direct or indirect communication between two ormore elements, whether or not those elements are in physical contactwith one another. The terms “include” and “comprise,” as well asderivatives thereof, mean inclusion without limitation. The term “or” isinclusive, meaning and/or. The phrases “associated with” and “associatedtherewith,” as well as derivatives thereof, may mean to include, beincluded within, interconnect with, contain, be contained within,connect to or with, couple to or with, be communicable with, cooperatewith, interleave, juxtapose, be proximate to, be bound to or with, have,have a property of, or the like.

While this disclosure has described certain embodiments and generallyassociated methods, alterations and permutations of these embodimentsand methods will be apparent to those skilled in the art. Accordingly,the above description of example embodiments does not define orconstrain this disclosure. Other changes, substitutions, and alterationsare also possible without departing from the spirit and scope of thisdisclosure, as defined by the following claims.

1. A method encoding of including at least one logical block address ina low density parity check (LDPC), the method comprising: selecting aLDPC Code matrix and a parity check matrix, wherein the LDPC Code matrixand the parity check matrix have an orthoginal relationship; encoding alogical block address (LBA) using at least some of the LBA bits in theparity bits in a LDPC codeword; and creating a parity vector using theat least some of the LBA bits in the LDPC codeword.
 2. The method ofclaim 1, wherein the LBA is a 40 bit field.
 3. The method of claim 1,wherein the method further comprises using a LDPC encoder to take anoutput of an error detection and correction block with the LBA specifiedas an input to both the LDPC encoder and the error detection andcorrection block.
 4. The method of claim 3, wherein the LDPC encodergenerates a parity as normal use data and appends the parity to bewritten to at least one computer readable medium.
 5. The method of claim4, wherein the LBA field is not written to the at least one computerreadable medium.
 6. The method of claim 1, wherein the LBA is providedduring a write operation.
 7. The method of claim 1, wherein creating aparity vector requires both the LBA and a plurality of circulantmatrices.
 8. A method of decoding at least one logical block address ina low density parity check (LDPC), the method comprising: receiving atleast one data element; resolving at least one parity vector using anexpected logical block address (LBA) to obtain at least one decodedlogical block address; verifying that the parity vector converges usinga de-interleaved soft output Viterbi algorithm (SOVA) extrinsicinformation; and comparing the decoded LBA with the expected LBA.
 9. Themethod of claim 8, wherein a fault message is sent to a host when theparity vector does not converge.
 10. The method of claim 8, a fault issent to the host when the decoded LBA does not match the expected LBA11. The method of claim 8, further comprising sending a decided codewordto an error detection and correction syndrome check.
 12. The method ofclaim 8, wherein the LBA is a 40 bit field.
 13. The method of claim 8,wherein the LBA is provided during a read operation.
 14. The method ofclaim 12, wherein for 512 byte sectors, 40 bits are used to identifyeach sector.
 15. The method of claim 12, wherein for 4 kilobyte sectors,38 bits are used to identify each sector and 2 bits are used to identify1 kilobyte blocks within the sectors.
 16. A system for encoding at leastone logical block address in a low density parity check (LDPC), thesystem comprising: a LDPC encoder configured to select a LDPC Codematrix and a parity check matrix, wherein the LDPC Code matrix and theparity check matrix have an orthoginal relationship, wherein the LDPCencoder encodes a logical block address (LBA) using at least some of theLBA bits in the parity bits in a LDPC codeword and creates a parityvector using the at least some of the LBA bits in the LDPC codeword. 17.The system of claim 16, wherein the LBA is a 40 bit field.
 18. Thesystem of claim 16, wherein the LDPC encoder is further configured totake an output of an error detection and correction block with the LBAspecified as an input to both the LDPC encoder and the error detectionand correction block.
 19. The system of claim 18, wherein the LDPCencoder is further configured to generate a parity as normal use dataand append the parity to be written to at least one computer readablemedium.
 20. The system of claim 16, wherein the LBA is provided during awrite operation.